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application note tda9102c AN540/0393 by f. grilli / p. berger technical information page 1. abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 2 2. introduction. . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 2 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . ................... 2 3.1 horizontal oscillator. . . . . ............................. ................... 2 3.2 horizontal synchronism shaper circuit. . . . . . . . . . ............................. 2 3.3 first phase comparator ( j 1) and phase adjustment interface circuit . . . . . . . . . . . . . . . 2 3.4 second phase comparator ( j 2) between flyback and oscillator . . . . . . . . . . . . . . . . . . 5 3.5 phase shifter, output stage and start up circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.6 voltage regulator 8v . ................................................... 6 3.7 vertical oscillator . ...................................................... 6 3.8 s correction circuit and dc linearity adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.9 vertical amplitude regulation circuit. . . . . . . . . . . . . . . . . . ....................... 8 4. conclusion . .................................... ................... 8 application information page 5. horizontal section . . . . . . . . . ....................................... 10 5.1 frequency . . . . . . . . . ................................................... 10 5.2 pull-in range . . . . . . . . . . . . . . . . . . . ....................................... 10 5.3 internal sync width . . . . . . . . . . . . ......................................... 10 5.4 phase adjustment range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................... 10 5.5 flyback input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................. 11 6. vertical section . . . . . . . . . . . . ....................................... 11 6.1 frequency . . . . . . . . . ................................................... 11 6.2 pull-in range . . . . . . . . . . . . . . . . . . . ....................................... 11 6.3 amplitude adjustment range . .......................... ................... 12 6.4 vertical dc reference . . . . . . . . . . . . ....................................... 12 6.5 linearity correction . . ................................................... 12 7. lay-out hints. . . . ................................................... 12 8. adjusting procedure . . . . . ......................................... 12 8.1 horizontal frequency . . . . ............................. ................... 13 8.2 vertical frequency . . . . . . . . . . . . . ......................................... 13 8.3 vertical amplitude and horizontal phase . .................................... 13 8.4 vertical linearity. ....................................................... 13 9. component list . ................................... ................ 15 1/15
1. abstract the system evolution in the monitor field leads to develop suitable i.c.'s whose performances and characteristics are mainly monitors oriented rather than tv oriented. the automaticfrequencies raster preset of the monitor by computer and optical equipments leads to the adoption of digital to ana- log converters in order to set the different parame- ters, and consequently all regulation must be dc compatible. high scanning frequency and low jitter are addi- tional factors that characterize the quality and the resolution of the monitor. in this note new circuit solutions on silicon, concerning the monitor field, are described. in a single i.c., making use of ttl compatible synchro pulses, horizontal and vertical processing functions and vertical ramp generation are implemented. 2. introduction in figure 1 is shown the block diagram of tda9102c. horizontal frequency and phase as well as vertical frequency, amplitude and linearity are all dc ad- justable on different terminals.the ho rizontal phase adjustment within 45 is implemented on first pll (sync-oscillator) rather than on the second pll (flyback-oscillator) allowing the raster to be centered in case of no standard phase sync posi- tion. an additional feature makes the raster phase inde- pendent by the duty-cycle of the input synchroniz- ing pulse thanks to an internal shaper circuit generating a standard sync pulse starting from the leading edge of input signal. the vertical amplitude changes depending on a voltage amplifier whose gain is set on pin 16 ; the peak to peak voltage of the sawtooth does not influence its average value which is maintained constant. the current capability of the horizontal output stage (pin 7) is such to directly drive an external dar- lington used as line power switch. since part of the jitter effect is due to the internal voltage reference circuits, an external pin con- nected to the v co supply voltage is got available for noise filtering (pin 19). 3. functional description here following are briefly described all the func- tional blocks of tda9102c. 3.1 horizontal oscillator the circuit in figure 2 is a current controlled oscillator, it works charging and discharging the capacitor at pin 2 between two thresholds v s1 = 2.5v and v s2 = 6.5v coming from an internal resistor divider. this one is also used to provide a voltage reference at pin 1 (v 1 = 3.5v) by means of a unity gain amplifier. an external resistor connected between pin 1 and ground sets the current reference. this current is mirrored with 0.5 : 1 ratio to charge the capacitor c o at pin 2, and with 2 : 1 ratio to discharge c o . the charging and discharging time ratio will result in 3 : 1. the differential switch q 22 -q 23 is driven by a s-r flip-flop, which changes its state every time that the peak of the triangular waveform reaches one of the two thresholds v s1 or v s2 . 3.2 horizontal synchronism shaper circuit the electric diagram shown in figure 3 can be divided in three stages. the first of which is a negative edge detector able to set the s-r flip-flop each time that a negative edge of the sync pulse is applied to the input (pin 4). the second one is a differential stage that feeds the first phase comparator ( j 1). the third stage uses an external capacitor to pro- duce a ramp on the pin 5. as soon as the peak of the ramp reaches the internal threshold (6v) the external capacitor is suddenly discharged and the flip-flop is reset. the horizonal sync pulse width on the collector of q 59 will depend on the value of the capacitor at pin 5. 3.3 first phase comparator ( j 1) and phase adjustment interface circuit in the circuit of figure 4, a comparator squares the horizontal waveform using as voltage reference vref1 which represents the output of the phase adjustment interface circuit. if the voltage at pin 10 changes in the range from 0.5v to 4.5v, the phase will shift of 45 between the sync and the middle of h-sawtooth (conse- quently middle of h-flyback). the rectangular waveforms that are the outputs of first differential amplifier are applied to another differential stage which is activated only during the internal horizontal sync pulse coming from the hori- zontal sync shaper circuit (see figure 3). the product in terms of current of the sync signal and the oscillator signal is available at pin 3. two clamps limit the maximum voltage range of pin 3 (from 1v to 6v) and consequently the hold in range of the cco. technical information application note 2/15
9102002.eps figure 1 4 15 5 698141718 16 13 12 10 3 1 2 11 20 19 horizontal flyback input vertical sync. input dc vertical linearity adjustement dc frequency preset dc vertical amplitude adjustement dc frequency adjustement dc horizontal phase adjustement horizontal sync. input +5v +5v v s v ref tda9102c v s voltage regulator vertical oscillator j 2 phase comparator vertical ttl interface low supply voltage protection horizontal oscillator j 1 phase comparator horizontal ttl interface hor. pulse shaper r3 c3 c1 r2 r1 c2 r12 r18 c18 c13 c9 r8 r14 7 c5 r4 application note 3/15
9102017.eps figure 2 4 5 v ref 6v s r q q q59 q60 sync i5 t t t 6v vpin4 vpin5 internal sync pulse 9102018.eps figure 3 9102019.eps figure 4 application note 4/15
9102020.eps figure 5 3.4 second phase comparator ( j 2) between flyback and oscillator this circuit recovers dynamically the deflection de- lay of line output transistor. the flyback pulse applied to pin 8 (see figure 5) is detected and clamped at a voltage level of 0.7v. this circuit is similar to j 1, the substantial differ- ences are two, the input pulse is the flyback pulse instead of sync pulse and the first differential stage is activated by s-r flip-flop of horizontal oscillator. the j 2 output acts on the horizontal output stage in order to shift the output pulse to recover the deflection delay. 3.5 phase shifter, output stage and start up circuit the storage time t s of the line output transistor is recovered by advancing the leading edge of the output pulse of ts with respect to the phase of the sync reference. the triangular oscillator waveform (figure 6a) is compared with internal threshold s 1 and s 2 whose voltages depend upon the voltage level present at the output of phase comparator j 2 (pin 9). the voltage difference s 1 -s 2 is constant and this value fixes the duty-cycle of the horizontal output pulse present at pin 7. during the positive slope of the oscillator the output pulse (pin 7) is low when the triangular waveform voltage is in the voltage range established by s 1 and s 2 ; whereas during the negative slope of the oscillator the output pulse is always at high level thanks to a comparator driven by s-r flip-flop of horizontal oscillator. as shown in figure 6a, a transistor insures that the output pulse is low when the flyback pulse is pre- sent (this feature can be used to simplify x-ray protection). at the switch on, the horizontal output stage (pin 7) is inhibited until the power supply does not over- come 8 v. about the maximun allowable delay, it depends on the flyback time and the working frequency (see figure 6b). the pll2 works in such a way as to maintain the middle of the flyback exactly in correspondence with the crossing between of the v ref = 4.5v and the oscillator ramp. then if you suppose to have zero delay time, the switch-off edge of the output pulse will rise at point oao now if the delay time increases the switch-off edge will move to point obo to recover the delay. the equation to calculate the t d with a good ap- proximation is the following : maximum allowable delay : t d = t r 2 - t fly 2 where t r is the rise time of the horizontal ramp = 3/4 t and t fly is the flyback time. the typical value of the horizontal duty cycle of the tda9102c is 41%. application note 5/15
a b oscillator ramp flyback pulse t t 6.5v 4.5v 2.5v output pulse (pin 7) d r off off 9102022.eps figure 6b 3.6 voltage regulator 8 v the voltage reference, figure 7, is a band-gap circuit that allows on the output a voltage reference equal to 2.622v that means a voltage v l =8v. 9102023.eps figure 7 9102021.eps figure 6a by means of zener zap is possible to adjust, during the testing, the voltage reference from 6% into a 2% range. v l feeds all the circuits of the vertical side and, by means of a unity gain amplifier, provides a voltage reference (v ref ) at pin 19 to supply all the circuits of the horizontal side. the unity gain amplifier is necessary to avoid all the possible interactions between the horizontal and vertical sections. moreover, to minimize jitter on the horizontal oscil- lator, is possible to connect an external capacitor between pin 19 and ground. 3.7 vertical oscillator a new concept of vertical oscillator is implemented in this i.c. whose resistor divider, used to set the lower and higher thresholds (v low =2v; v high = 6.8v), is not commutated . the circuit shown in figure 8 works charging an external capacitor connected at pin 13 with a cur- rent set at pin 12 and reflectd to pin 13 through a current mirror. as soon as the ramp gets v m or v high the capacitor is quickly discharged by a darlington, the voltage on the capacitor will fall down till to get the lower threshold; at this point the darlington will be driven off and the current will charge again the capacitor. a buffer is used to decouple the ramp generator from other circuits (like linearity correction and amplitude regulation circuits). the lower threshold is detected by a differential stage whose current generator is only activated during the discharge phase. application note 6/15
9102024.eps figure 8 a comparator detects the higher threshold corre- sponding to the free running frequency; if no sync pulse (negative edge) is applied on pin 14, this stage is continually fed and the capacitor at pin 13 is discharged when the vertical ramp reaches v high . if the sync pulse is present the previous comparator will be inhibited and another comparator, which has the threshold at 5.2v (v m ), will be activated. this last comparator, when it is set going, is able to cause the discharge of the capacitor at pin 13 if the vertical ramp is between the thresholds vm and v high . in this way the vertical synchronization is estab- lished. to guarantee that the vertical oscillator is locked in the middle of the pull-inrange is necessary to adjust the current at pin 12 until the peak of the vertical sawtooth, in locking condition, reaches the voltage equal to: v p = v m + v high 2 = 6v that means v pp =4v. 3.8 s correction circuit and dc linearity ad- justment the circuit which is used to realize a new concept of vertical linearity regulation is shown in figure 9. a comparator rectifies the vertical sawtooth using as voltage reference a fixed value (4v) that is the average value of sawtooth. this squared signal is used to drive a particular configuration of differential stage in order to obtain, in terms of current, a triangular waveform which inverts its slope just when the original sawtooth crosses the voltage reference. 9102025.eps figure 9 application note 7/15
9102026.eps figure 10 this current signal is converted in voltage by a resistor divider and transferred on pin 18 through a buffer. the peak to peak voltage on this pin depends on the maximum current that the output differential stage is able to handle, the value of this current can be externally regulated by means of pin 17 through a transconductance amplifier. an external feedback resistor in series to a capaci- tor (to avoid any dc offset) must be connected between pins 18 and 12 in order to obtain the proper s correction as shown in figure 10. 3.9 vertical amplitude regulation circuit this function has been implemented using the circuit configuration that can be seen in figure 11. it consists of an op-amp in non inverting input configuration and of a variable gain ota whose gain can be set by means of the pin 16 through a transconductance amplifier. both the inputs of the two circuit handle the vertical ramp and the output of the multiplier is fed back to the inverting input. the control circuit is a transconductanceamplifier that modulatesthe current of the variable gain ota depending on the dc voltage applied on pin 16. this circuit guarantees a gain adjustment of 20% around the nominal value. 4. conclusion this new i.c. can be considered as a first step towards a new generation of serial bus compatible lsi circuits in which additional logic function can be implemented and all the d/a converters can be included. it is assembled in 20 pins dil plastic package able to dissipate the 0.7w required by a typical applica- tion. 9102027.eps figure 11 application note 8/15
application information in figure12 is shown a typical application of the tda9102c with the tda8172, which is a vertical booster; for further information regarding tda8172 consult the note : sgs-thomson overtical deflection stages for tv and monitoro by a. messi all the information is referred to the above men- tioned figure. 414 17 16 5 8 9 10 20 7 6 19 15 18 12 1321113 hor. sync. vert. sync. fly. input 7 2 6 3 5 4 1 tda8172 hor. out vert. yoke v 14v s r10 22k w c9 100nf c8 100 m f r11 22k w r12 10k w c15 1 m f r20 150k w r21 62k w r22 220k w c16 220nf c17 1.8nf c18 15nf c19 2.2 m f r23 3.3k w r24 56k w r25 6.8k w p4 47k w p5 47k w c20 22nf r27 100k w c21 0.22nf r29 2.2k w r28 2.2k w r1 3.3k w r2 3.3k w r3 51k w p1 47k w r4 22k w p2 47k w r5 39k w c3 15nf c4 15nf c5 15nf r7 39k w p3 47k w c1 100nf c2 470 m f c6 100nf c7 1000 m f d1 1n4001 c10 220 m f c14 10 m f r18 1.2k w r17 2.7k w c13 47 m f r15 1.5k w r14 1.5 w r13 120 w c12 220nf c11 2200 m f r16 1 w oco correction r9 82 w 2w ic3 vv o i g n d ic1 7812 r6 5.1k w r8 5.1k w r26 22k w r19 47k w * note : * the value of r19 dependson crt. on the mock up r19 is substitued with a resistance+ trimmerfor generic applications. hor. power gnd tda9102c ic2 9102005.eps figure 12 application note 9/15
5. horizontal section 5.1 frequency the device is able to work from 15khz to 100khz. the free running frequency is fixed by the resistor at pin 1 (r 25 ) and by the capacitor at pin 2 (c 17 ) with the following formula: f o = 1 k o xr 25 xc 17 where k o is typically 3.0476 5% (see data-sheet). in the aplication of figure 12, using r 25 = 6.8k w and c 17 = 1.8nf, we obtain: f o = 10 6 3.0476 x 6.8 x 1.8 = 26.808khz the maximum available current at pin 1 is 1ma, so it must be v 1 r 25 1ma. by means of trimmer p 4 , it is possible to adjust the horizontal free running frequency, that changes accordingly with the following formula: f h = f o ? ? ? 1 - ( v p - v 1 ) /r 26 v 1 /r 25 ? ? ? where 0 v p 8v is the voltage at the central point of the trimmer (see figure 13). 1 v ref p p i ab p v a b p=p+p 4 r r 26 25 9102028.eps figure 13 5.2 pull-in range this range is determined by the ability of the first comparator ( j 1) to correct the difference between the sync frequency and the free running frequency and it is set by r 24 and r 25 . f pull - in = f o |v 3 - v 1 | /r 24 v 1 /r 25 |v 3 -v 1 | is typically 2.5v, while v 1 = 3.5v. this is the theoretical value calculated if the fre- quency adjustment is disconnected. in the application inf figure 12 we have: f pull - in = 26808 2.5 3.5 ? 6800 56000 = 2.3khz when the frequency adjustment is connected the pull-in range changes due to the fact that in parallel with r 25 are connected r 26 +p b (see figure 13). when the device is synchronized and perfectly tuned, v 3 =v 1 and the j 1 will work in the best way. c 17 , on the contrary of r 25 , is influential only for the free running frequency of the horizontal oscillator; it has no effect on the pull-in range, which doesn't change in percentage with respect to the free run- ning frequency. if you change the horizontal frequency changing r 25 the pull-in range changes accordingly with the previous formula. 5.3 internal sync. width the internal sync. pulse is made by current gener- ator (i 5 ) that charges an external capacitor at pin 5 (c 21 ) up to the trigger threshold v 5 =6v. t 5 = c 21 x v 5 i 5 t 5 = 1 / (12 x f o ) is recommended. 5.4 phase adjustment range the voltage range accepted at pin 10 is from 0.5v to 4.5v,so the resistor divider must be dimensioned to supply these values. in our application we have : v 10 min ? ? ? ? ? ? ? ? ? = v 19 r 7 + p 3 + r 8 r 8 = 8 39 + 47 + 5.1 5.1 = 0.447v v 10 max ? ? ? ? ? ? ? ? ? = v 19 r 7 + p 3 + r 8 ( p 3 + r 8 ) = 8 39 + 47 + 5.1 52.1 = 4.575v application note 10/15
v ref p p i ab p v a b p=p+p r r 5 22 21 12 c 13 c i c 16 9102029.eps figure 14 v v v v t 1 1 t f f osc m high low s max v 9102030.eps figure 15 5.5 flyback input the resistor in series at pin 8 (r 27 ) must be dimen- sioned in order to have an input current included between 0.7maand 2ma (typ 1ma), according with the following formula: r 27 = v fly - 0.6 v 1ma 6. vertical section 6.1 frequency the device is able to work form 30hz to 120hz. the free running frequency is fixed by r 21 and c 16. the formula to calculate the free running frequency is the following: f v = i c ( v high - v low ) xc 16 but i c = i = v 12 r 21 0.5ma then f v = v 12 ( v high - v low ) x c 16 x r 21 where v 12 = 3.5v, v high = 6.8v and v low =2v. in the application proposed the free running fre- quency is: f v = 3.5 x 10 6 ( 6.8 - 2 ) x 220 x 62 = 53.4hz with the trimmer p 5 is possible to change the current that charges c 16 and consequently to change the free running frequency. the current in c 16 due to this correction become: i c = v 12 r 21 - v p - v 12 r 22 where 0 v p 8v is the voltage at the central point of the trimmer (see figure 14). it is easy to substitute the new i c in the formula in order to obtain the new free running frequency. 6.2 pull-in range the vertical pull-in range is fixed by internal thresh- olds. with reference to figure 15 : we can write : f pull - in =f max -f v f max = 1 t v - t s t s = ( v high - v m ) ( v high - v low ) xt v = k 14 xt v the value of k 14 is 0.333 (see data-sheet). application note 11/15
6.3 amplitude adjustment range the voltage range accepted at pin 16 is from 0.5v to 4.5v. so the resistor divider must be dimensioned to supply these values. in our application we have: v 16min ? ? ? ? ? ? ? ? ? = v 19 r 5 + p 2 + r 6 r 6 = 8 39 + 47 + 5.1 5.1 = 0.447v v 16max ? ? ? ? ? ? ? ? ? = v 19 r 5 + p 2 + r 6 ( p 2 + r 6 ) = 8 39 + 47 + 5.1 52.1 = 4.575 v this system allows a vertical ramp amplitude vari- ation of 20% around the nominal value; the value of amplitude of vertical ramp at pin 15 can be determined with the following formula: v 15 pp =[k 16 (v 16 - 2.5) + k 15 ]v 13pp where k 15 is typically 1 and k 16 is typically 0.1 (as you can see on the data-sheet). 6.4 vertical dc reference the average value of the vertical ramp at pin 15 is the half of v 19 , then with a resistive divider this dc voltage can be used as reference for the vertical booster as shown in figure 12. for a best noise immunity we suggest to filter v 19 with an electrolytic capacitor. 6.5 linearity correction the oso correction is performed with the new con- cept described in chapter 3.8. the adjustment is obtained varying the dc voltage at pin 17 from 1.5 to 4.5v, then the resistor divider (r3, p1 and r4) must be dimensioned for obtaining this range of values. in our application we have: v 17min ? ? ? ? ? ? ? ? ? = v 19 r 3 + p 1 + r 4 r 4 = 8 51 + 47 + 22 22 = 1.466 v v 17max ? ? ? ? ? ? ? ? ? = v 19 r 3 + p 1 + r 4 ( p 1 + r 4 ) = 8 51 + 47 + 22 69 = 4.6v the oso correction is not performed when the volt- age at pin 17 is 1.5v, while it is maximum when the pin 17 voltage is 4.5v. you can verify this using the following formula: v 18pp =k 18 (v 17 - 1.5) where k 18 is typically 1. if the crt requires a higher oso correction, it is possible to obtain it reducing the value of r 20 ; however take care that c 15 in series with r 20 is a high-pass filter with the purpose to cut only the dc. in our application we have: f t ? ? ? ? ? ? ? ? ? = 1 6.28 x r 20 x c 15 = 10 3 6.28 x 150 x 1 = 1.06 hz the oco correction is obtained with a resistor in series to a capacitor connected between pin 15 and the central point of the vertical dc feedback of vertical booster (r 19 and c 14 ). the value of r 19 is strictly dependenton crt used. 7. lay-out suggestions it is necessary to take care not to connect the horizontal output ground (pin 6) directly to pin 11, to avoid horizontal interference on vertical stages. the 15nf capacitors connected on pins 10, 16 and 17 have the only aim to filter the dc control voltage against horizontal noise, so they must be con- nected as close as possible to the above men- tioned pins. 8. adjusting procedure here following it is shortly described the procedure to adjust horizontal and vertical frequencies, verti- cal amplitude, linearity and horizontal phase. before starting these operations take care that the horizontal and vertical synchronization pulses are properly applied to the device inputs. application note 12/15
v v osc m high v (v) 6 ramp at pin 13 vertical sync. 9102031.eps figure 16 8.1 horizontal frequency adjust p 4 in order to obtain v 3 =v 1 ; in this way the horizontalsynchronisation is perfect, and the pull-in range is maximum in both directions. 8.2 vertical frequency adjust the vertical ramp amplitude using p 5 in order to have 4v pp ; in this way the vertical frequency value is in the middle of the synchronization range; as shown in figure 16. this operation is important because some internal circuits are dimensioned for a 4 vpp ramp. 4v gnd ramp at pin 13 vertical scan yoke current waveform at pin 18 t sc t c t t s v 9102032.eps figure 17 8.3 vertical amplitude and horizontal phase looking at the display correct p 2 for the right verti- cal amplitude and adjust p 3 in order to have the correct horizontal phase. 8.4 vertical linearity if the vertical ramp at pin 13 is correctly set the central point of the omo waveform at pin 18 will be at the center of the scan; in other case, using p 5 , lead the central point of omo in correspondence of the scan center (see figure 17). where : t s = scan time t v = 1/f v = vertical period t sc = scan centre t c = period centre in this way the s linearity correction has a uniform behaviour on the top and bottom sides of the crt. now looking at the display, adjust p 1 to obtain a right s correction and select r 19 value to optimise the c correction. application note 13/15
9102033.tif figure 18 : solder side 9102034.tif figure 19 : component side application note 14/15
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without noti ce. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system confo rms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 9102035.tif figure 20 : pcb layout 9. component list component value component value component value r 1 ,r 2 ,r 23 3.3k w r 20 150k w c 10 220 m f / 25v r 3 51k w r 21 62k w c 11 2200 m f / 16v r 4 ,r 10 ,r 11 ,r 26 22k w r 22 220k w c 12 ,c 16 220nf r 5 ,r 7 39k w r 24 56k w c 14 10 m f / 63v r 6 ,r 8 5.1k w r 25 6.8k w c 15 1 m f r 9 82 w /2w r 27 100k w c 17 1.8nf r 12 10k w r 28 ,r 29 2.2k w c 19 2.2 m f / 63v r 13 120 w p 1 ,p 2 ,p 3 ,p 5 ,p 6 47k w hor. c 20 22nf r 14 1.5 w p 4 47k w ver. c 21 220pf r 15 1.5k w c 1 ,c 6 ,c 9 100nf d 1 1n4001 r 16 1 w c 2 ,c 13 470 m f / 16v ic 1 l7812 r 17 2.7k w c 3 ,c 4 ,c 5 ,c 18 15nf ic 2 tda9102 r 18 1.2k w c 7 1000 m f / 25v ic 3 tda8172 r 19 33k w c 8 100 m f / 16v 9102006.tbl application note 15/15

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